Devices

[ electrical circuits and systems ] circuit voltage switch input delay current output switching line interconnect capacitance switches stage load noise coupling power energy chip driver gate response design inductor converter resistance ground buffer capacitor cmos proposed victim waveform substrate transmission analysis inductance lines equivalent wire source

[ electrical devices ] power amplifier circuit current noise output device gain transistor voltage efficiency ghz devices mixer input frequency low bias measured microwave design technology performance distortion impedance electron base sige signal gate source bipolar hbt linearity mhz nonlinear conversion resistance emitter theory frequencies due trans

[ computer hardware testing ] test fault scan core output testing circuit input coverage logic processor chain proposed bit path generation transition chip design cores methodology defect test_vector hardware system area instruction constraint power crosstalk program embedded techniques pattern compaction memory overhead xor configuration scheme reduction

[ complexity analysis ] log location random bit function probability input complexity sample_size qtl pair protocol xjy def entropy communication equal generator circuit string cim distribution output spacing worst_case lower_bound length threshold deterministic oracle depth messages transmitted pseudo dlog transmit boolean polynomial_time message hard i

[ graph partitioning algorithms ] partitioning partition cut local cost bisection search gain algorithm heuristic optimization random placement graph cluster quality run move average instances net clustering annealing design improvement experiment global circuit instance netlist crossover benchmark hypergraph implementation ordering fixed modules rent vlsi initial

[ computer hardware ] design behavior bus system communication port architecture channel hardware data specc specification synthesis type interface statement signal protocol list implementation software memory void tool main clock event refinement designer code layer window execution rtl timing language bit simulation chapter input step mapping unit in

[ circuit design ] delay design net placement routing layout sink cost fill wirelength area density layer skew minimum timing steiner wire length window total pin budget merging edge interconnect optimal buffer block slack clock dme technology driven path constraint mask flow global elmore terminal cell performance vlsi maximum kahng topology linear